hardware multiplication
1.This article provides a brief description of RSA public key cryptography, an analysis and compare of all kinds of present existed modular exponentiation in RSA public key cryptography, a colligation of the fastest accelerating software algorithm-VLNW sliding window methods and hardware mapping fast Montgomery modular multiplication algorithm that can improve the implementary efficiency of RSA public key cryptography for achieving the novel algorithm-Mnexp algorithm.
3.Researching the domestic and external development status of robot, we forward a hardware structure basing on DSP and Complex Programmable Logic Device (CPLD). CPLD is used to accomplish the direction decoding, four frequency multiplication and counting for two quadrature encoder pulse.
4.2) A recursive algorithm has been proposed in the original paper for VLSI(Very Large Scale Integration) implementation of EIDCT, but it takes a large number of operations and the hardware cost is rather high, so two new hardware implementation algorithms of EIDCT and the corresponding architectures are propounded from the aspect of lowering the computational complexity, which drastically reduces the numbers of multiplication and addition needed, constructing a basis for the future chip design(cf. : Chap. 4).
5.In this article we modify one-dimension systolic array implementation of Montgomery modular multiplication (MMM) and present a circle-like architecture, called the Circular Structured Systolic Array (CSSA) for hardware imple-mentation of MMM.
