loop gain
4.Results show that it has achieved an open-loop gain of 125 dB, a CMRR of 120 dB, an offset voltage of 18 μV and a slew rate of 0.6 V/μs.
7.The Op-amp utilizes a PMOS bulk-driven differential pair to achieve 0.8 V operation while providing a dc open-loop gain of 74 dB, phase margin of 66° and the input offset voltage of 940 μV with 110~(798 mV) output voltage swing.
8.Based on the analysis of the principle, electric characteristic and equivalent circuits of quasi floating-gate transistors, a novel 0.8V OPA and 0.8 V Rail-to-Rail analog switch are proposed in TSMC 0.25μm 2P5M CMOS technology,the DC open-loop gain of the amplifier is 76.3dB, the phase margin is 75° and the unit gain width is 1.05 MHz.
9.In 1.6μm N-well BiCMOS process, simulation in HSPICE showed that, the design realized a CM range VCM reaching+7 V at a single supply voltage 2.7V, while the supply power was 2.7V. The design of the operational amplifier resulted in the performances of 3MHz bandwidth (at 72.5 of phase margin),open loop gain 62.5 dB.
10.The chip has been realized in 0.35μm 2P4M CMOS technology. The amplifier features an open-loop gain of 83.9dB and a GBW of 10MHz. The measured typical residual input offset is less than 93.7μV,and the equivalent input low frequency noise is 19.6nV/Hz at a chopping frequency of 100kHz and supply voltage of 3.3V.
