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1.Rambus DRAM (RDRAM), a memory architecture that has been used for years in Nintendo gaming systems, is just now getting ready to move into computers.
Rambus DRAM(RDRAM),在Nintendo游戏系统中使用多年的存储器体系结构,现在准备进入计算机。收藏指正
2.RISC processors generally feature fixed-length instructions, a load-store memory architecture, and a large number of general-purpose registers and/or register windows.
RISC处理器一般的特征是固定长度的指令集,一个负载储备存储结构,和大量通用寄存器,及寄存器窗口。收藏指正
3.Based on the analysis of the SDRAM and DDR memory architecture,this paper presents the design principals of MBM and offers the implementation and the actual waveforms.
在详细分析了SDRAM和DDR存储器结构的基础上,提出了MBM的设计思想,并给出了其实现方法和实际波形。收藏指正
4.In order to resolve system’s memory problems, analyse and compare three memory architectures: DAS(Direct Attached Storage)、NAS(Network Attached Storage) and SAN(Storage Area Network), ultimately apply SAN memory architecture technology to the network management system of GuiZhou network communication Corporation successfully, satisfy the system’s requirements to the aspects of stability, expansibility, security and resource availability and so on.
为解决系统的存储问题,对DAS(Direct Attached Storage)、NAS(Network Attached Storage)及SAN(Storage Area Network)三种存储结构进行分析、比较研究,成功地将SAN存储结构技术应用于贵州网通网管系统的建设中,满足系统对存储网络的稳定性、可扩展性、安全性及资源利用率等方面的要求。收藏指正
5.NUMA: Non-Uniform Memory Access Architecture
NUMA:非均匀存储器存取结构收藏指正
6.Supported with most quantitative application software, CISC processor is one of the most widely used, while its memory management architecture is one of the most complex in contemporary general-purpose processors.
CISC处理器在实际应用中最为广泛,相关软件最为丰富; 但是它也有着现代微处理器中最复杂的存储管理单元。收藏指正
7.And a faster processor is useless unless the memory and bus architecture allows PCs to deliver data to the processor more efficiently.
除非存储器和总线的体系结构使PC机能更有效地向处理器输送数据,否则速度更快的处理器也没有用。收藏指正
8.Mm This directory contains all of the memory management code. The architecture specific memory management code lives down in arch/*/mm/, for example arch/i386/mm/fault.c.
与具体体系结构相关的内存管理代码位于arch/*/mm目录下,如arch/i386/mm/fault。c。收藏指正
9.The Research on Memory-Level Parallelism Execution Model in EPIC Architecture
EPIC微体系结构的存储级并行执行模型的研究收藏指正
10.In the circuit structure, the complex transfer memory is needless, but the architecture of parallel input and output is used, to complete N×N DCT transformations takes only N clock cycles, so that its throughput is N times as much as that of the traditional DCT.
该电路结构不需要复杂的转移存储器 ,而是采用平行输入平行输出的结构 ,完成一次N×N个DCT变换只需要N个周期 ,因此吞吐率是传统DCT的N倍。收藏指正
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