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1.FIFO memory controller based on VHDL design
VHDL语言实现FIFO存储控制收藏指正
2.An ASIC Design for Target Data Memory Controller
目标数据存储控制单元的ASIC化设计收藏指正
3.Using FPGA to Implement DDR Memory Controller Scien?
利用FPGA实现DDR存储器控制器收藏指正
4.5. A demo system with the name, uCRISC, is designed based on SRISC. The system consists of SRISC processor, Wishbone bus, memory controller, and otherperipherals.
5.设计了基于SRISC的演示系统uCRISC，该系统包括S班SC微处理器、Wishbone总线、内存控制器以及计时器、中断控制器等外设;收藏指正
5.It is designed for embedded applications with the following features: separate instruction and data caches (Harvard architecture), 5-stage pipeline, hardware multiplier and divider, interrupt controller, 16-bit I/O port and a flexible memory controller. New modules can easily be added using the on-chip AMBA AHB/APB buses.
它遵照IEEE-1745（SPARC V8）的结构，针对嵌入式应用具有以下特点：采用分离的指令和数据cache（哈佛结构），五级流水，硬件乘法器和除法器，中断控制器，16位的I/O端口和灵活的内存控制器，具有较强的异常处理功能，新模块可以轻松的通过片上的AMBA AHB/APB总线添加。收藏指正
6.In hardware design part, explains especially the interface of S3C2410 CPU chip with memory and network controller chip.
硬件部分重点论述了S3C2410 处理器与存储器和网络控制器芯片的接口设计问题。收藏指正
7.The system is mainly composed of NAND Flash Memory K9K1G08UOM, micro-controller AduC812, and USB interface device PDIUSBD12. The K9K1G08UOM is 128M byte sequential access device, which utilizes the I/O pins for both address and data input/output as well as for command inputs.
该系统主要由NAND型闪速存储器K9K1G08UOM、微控制器ADuC812和USB接口芯片PDIUSBD12构成。收藏指正
8.The third chapter shows the interface design schemes between DSP and CCD、CPLD 、flash memory and DMS voltage controller.
第三章具体研究数字信号处理模块中DSP 与CCD、CPLD、flash 存储器和变型镜电压控制器等部分的接口方案设计。 第四章详细介绍了波前处理的软件设计方案、开发平台和设计流程。收藏指正
9.A kind of network multi functional electric energy meter is introduced,which is composed of 80C196KC microprocessor,PSD913F2 flash memory and RTL8019AS net interface controller.
介绍了一种网络化的多功能电能表。 其硬件主要包括 80C196KC处理器、PSD913F2闪存和RTL80 19AS网络接口控制芯片等。收藏指正
10.The controller''s memory is a critical element in the ATC system.
管制员的记忆是ATC系统的一个重要组成部分。收藏指正
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