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1.This paper introduced the basic theory of sewing process layout of apparel production line and the process load balance,discussed the basic method to balance apparel production load,and analysed the process layout of jeans in practice.
介绍了服装生产线缝制工艺编排和工艺负荷平衡的基本理论,讨论了服装生产线负荷平衡的基本方法,并结合生产实际对牛仔裤的工序编排进行了分析。收藏指正
2.and give a method of how to improve production management for auto parts manufacturers through the case , analysis the status in quo of production management through interview and investigate ,data stat ,bench marking ,and conclude the main problems in dire need of solving :Under process layout ,the logistics are very complexity for many varieties, The distance to move is very far .
主要运用现场访问与观察、数据统计与分析、差异分析等方法对伟敏公司的生产管理现状进行了分析,指出了当前在生产管理方面急需解决的主要问题:生产布局基本上是按照生产流程布置,由于品种多,生产物流复杂,造成生产过程中运送距离较长。收藏指正
3.Optimize process and factory layout.
协助规划工厂布置,优化空间利用率。收藏指正
4.On Visual Process of Ads Layout Design for Newspapers
论报纸广告版面设计的视觉流程收藏指正
5.The high_speed stamping process and layout design of the tongue_box terminal and the structure of the progressive die for the part were stated. A practical bending device that switches the stamping direction and a locating device were introduced.
介绍了长舌箱体端子零件的高速冲压工艺、排样设计及级进模结构 ,还介绍了一种转换冲压方向的实用打弯装置和一种定位装置收藏指正
6.By improving on material growth design,process design and layout design,the maximum oscillation frequency of RTD has reached54GHz.
经过材料生长设计、工艺设计和版图设计几方面的改进,测得最高振荡频率已达54GHz。收藏指正
7.When circuit design and function verification had been finished, the physical design in Chartered 0.35 μm CMOS High Voltage process and post-layout verification were accomplished subsequently.
最终确定采用Chartered的0.35μm CMOS高压工艺顺利完成了芯片版图设计以及后仿真,进而完成芯片的全部设计。收藏指正
8.Simulation with 0.35 μm/3.3 V AMS Si-CMOS process models and layout show that the ADC achieves a DNL< ±0.4 LSB,INL< ±0.5 LSB,and an SFDR of 59.2 dB with 250 MSPS at Nyquist frequency.
0.35μm/3.3 V AMS Si-CMOS工艺模型和版图验证结果表明,在实现250 MSPS前提下,DNL<±0.4 LSB,INL<±0.5 LSB;收藏指正
9.Layout design process to meet the requirements.
装置布置设计应满足工艺流程的要求。收藏指正
10.This PLL is implemented based on a 0. 25-μm n-well CMOS process, the active area of layout is 600μm· 335μm.
有效版图面积为600μm·335μm.收藏指正
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