synchronous counter
1.The designed examples show that the method used to design the module? N+1 synchronous counter with cyclic code has the advantages of being easy and fast, and is of certain practical significance.
2.This paper discusses the advantages of PLD (programmable logical device) in designing a digital circuit,and at the same time,discusses how to realize a 6 bit synchronous up/down counter with clear by using PLD GAL16V8.
3.Its synchronous phase-shift function is produced by microcomputer auto-matically, the VFC and counter-gate act as a PSD, and fhe counter combin-ing with real time processing of smoothing act as the LPF.
4.On the basis of above theory, this paper presents a synthesis for adiabatic synchronous sequential circuits, and designs an adiabatic 5421BCD decimal counter circuit of 32 MOS transistors which consumes lower power than that of an adiabatic PAL-2N 4-bit binary counter. Above theory is vertified by computer simulation.
